Traditional silicon-on-insulator (SOI) integrated circuits are formed on SOI substrates. A cross-section of a silicon-on-insulator (SOI) substrate 100 is illustrated in FIG. 1a. SOI substrates typically have a thin layer of silicon 110, also known as the silicon active layer, disposed on an insulator layer 112 such as the buried oxide (BOX) layer. The insulator layer 112 or the buried oxide layer 112 is provided on a silicon substrate 114. The buried oxide 112 is comprised of an insulator such as silicon oxide. It electrically isolates the silicon active layer 110 from the silicon substrate 114.
In an SOI chip, as shown in FIG. 1b, the SOI substrate 100 is processed to form a plurality of active regions 116 in the active layer 110. Active devices 118 such as transistors and diodes may be formed in the active regions 116. Active regions 116 are electrically isolated from each other by isolation regions 120. The size and placement of the active regions 116 are defined by isolation regions 120. Isolation regions 120 may, for example, be formed of shallow trench isolation (STI). Moreover, active devices 118 in the active regions 116 are isolated from the substrate 114 by the buried oxide layer 112.
Active devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption. At present, commercial products using SOI technology employ an uniform active layer thickness and shallow trench isolation.
One type of SOI transistor employs a very thin silicon active layer 110. In some cases, the silicon active layer 10 thickness can be as thin as a third of the gate length. For example, if the gate length is 30 nm, the silicon active layer 110 may have a thickness of 10 nm or thinner. This type of SOI transistor is known as an ultra-thin body (UTB) transistor or a depleted-substrate transistor (DST).
When the thickness of the silicon active layer 110 is as thin as 10 nm, mesa isolation could be a more appropriate isolation scheme for the transistors as compared to shallow trench isolation. In mesa isolation, trenches 122 are formed in the active layer 110, as shown in FIG. 2a. The trenches 122 extend from the surface of the active layer 110 to the buried oxide 112. The trenches 122 divide the active layer 110 into silicon islands or silicon mesa structures that include the active areas 116. The mesa isolation method thus cuts electrical connection between adjacent active regions 116 by removing portions of the active layer 110 in the SOI substrate 100.
One problem of the mesa isolation is that the exposed buried oxide layer 112 surface will be recessed in subsequent chemical treatments such as wafer cleaning steps. This recess is illustrated in FIG. 2b. The recessed buried oxide results in a number of problems. For example, it leads to an increased parasitic capacitance between the substrate 114 and metal lines (not shown) running over the buried oxide 112. It also leads to a concentration of electric field lines around the exposed corners of the silicon mesas which potentially impact device reliability.